Architectures for Computer Vision_ From Algorithm to Chip with Verilog

Architectures for Computer Vision_ From Algorithm to Chip with Verilog

Author: Jeong [2014-10-13]

1. Introduction
2. Verilog HDL, Communication, and Control
3. Processor, Memory, and Array
4. Verilog Vision Simulator
5. Energy Function
6. Stereo Vision
7. Motion and Vision Modules
8. Relaxation for Energy Minimization
9. Dynamic Programming for Energy Minimization
10. Belief Propagation and Graph Cuts for Energy Minimization
11. Relaxation for Stereo Matching
12. Dynamic Programming for Stereo Matching
13. Systolic Array for Stereo Matching
14. Belief Propagation for Stereo Matching

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Algorithms 11:03 PM